Phase-Locked Loop System and Circuit Design for Clock generation

Designed a complete PLL system for 2.56GHz clock generation at transistor level. Simulated and optimized performance of PLL for key metrics like spur rejection, power supply rejection, phase noise with nominal loop gain and phase margin. This project was done under the guidance of Prof. Saurabh Saxena, for the course EE6324 – Phase Locked Loops.